In complementary metal oxide silicon (CMOS) structures a well known parasitic effect occurs between a pair of cross-coupled parasitic pnp and npn bipolar transistors which form a positive feedback path. The current gain in the two transistors can reach a point in which a circuit is easily triggered by an external disturbance such that it creates a regenerative condition and the transistors are driven by each other. The current in both transistors can increase until they self limit or until they lead to the destruction of an integrated circuit. This condition, known as latch-up, can occur when a back bias generator is contained in an integrated circuit and the integrated circuit is powered on. During power-on, the back bias generator voltages are not clearly defined, the well regions are not biased to the correct levels, and hence under such conditions latch-up is likely to occur. The back bias generator is useful, however, during integrated circuit stand-by mode when it reduces the transistor subthreshold current by applying a bias voltage to the well regions to establish greater threshold voltages than during the active mode of operation. For example, in modem deep sub-micron process technology, MOS transistor threshold voltage is usually in the range of 0.25 volts to 0.4 volts. With such threshold voltage and leakage worst operating condition (e.g., high temperature and fast process comer), transistor drain leakage at its off state can occur in the range of several tens of nano-amperes per unit size. The total leakage can increase to a problematic level, especially in battery-powered applications, with the use of many transistors (i.e., for an integrated circuit such as microprocessor, the total leakage of hundreds of mA can occur). Therefore, the back bias generator is used to bias the well regions to increase the threshold voltage, significantly reducing transistor leakage during standby mode.
It is common practice to use a resistor 11 and a capacitor 12 in series, as shown in FIG. 1a, to provide an RC time constant which determines the amount of time required to reach a desired capacitor voltage on output terminal 13 from an applied source voltage on line 14. This type of resistor-capacitor (RC) circuit 10 is used to disable the back bias generator and force the integrated circuit into the active mode when the integrated circuit is initially powered on (i.e., "power on reset"). Capacitor 12 charges through resistor 11 when VDD is applied to the integrated circuit and discharges through resistor 11 when VDD is removed. RC circuit 10 provides an output terminal 13, a power-on-reset control signal according to the voltage versus time characteristics as shown in FIG. 1b. The problem with this prior art circuit is that a high value multi-mega ohm resistor 11 is necessary to obtain the desired RC time constant. This type of resistor is often unavailable in many types of fabrication processes.
A second prior art circuit widely used but still having shortcomings that are overcome by the present invention is shown in FIG. 2a. Here, PMOS transistor 21, having a long and thus highly resistive channel, is used in place of high resistance resistor 11 of FIG. 1a. When VDD is applied to lead 24, P channel transistor 21 turns on, charging capacitor 22, providing the power-on-reset signal shown in FIG. 2b. When VDD is removed from lead 24, capacitor 22 discharges to lead 24 through transistor 21 (now the drain and source reversed) and the PN junction formed between drain 21c and the well region of transistor 21. However, the discharging of capacitor though the PN junction stops when the voltage on capacitor 22 drops below the diode turn-on voltage and the discharging of capacitor 22 through transistor 21 stops when the voltage on capacitor 22 drops below threshold voltage of transistor 21. This is shown in the diagram of FIG. 2b. When VDD is switched on and the voltage on capacitor 22 is not zero, capacitor 22 charging time is severely decreased. Thus, the capacitance of capacitor 22 must be significantly increased to assure the desired RC time constant to provide an appropriate time period upon power-on-reset during which the back bias generator is disabled and the integrated circuit is placed in the active mode, thereby preventing latch-up. To assure the desired RC time constant using this circuit which provides the power-on-reset signal on output terminal 23, a large capacitance is needed. However, using a large capacitor increases the integrated circuit area and is thus expensive.